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| integrated circuit systems, inc. ics9148-111 third party brands and names are the property of their respective owners. block diagram 9148-111 rev a 10/19/99 functionality pin configuration 48-pin 300mil ssop recommended application: output features: ? 3 - cpus @ 2.5v/3.3v, up to 100mhz. 3 - agpclk @ 3.3v 13 - sdram @ 3.3v, up to 100mhz. 6 - pci @ 3.3v, including one free running. 1 - 48mhz, @ 3.3v fixed. 1 - ref @ 3.3v, 14.318mhz. features: up to 100mhz frequency support support power management: cpu, pci, agp stop and, power down mode from i 2 c programming. spread spectrum for emi control (0 to -0.6%, 0.25%). uses external 14.318mhz crystal fs pins for frequency select key specifications: cpu ? cpu: 250ps sdram - sdram: 250ps agp-agp: 250ps pci ? pci: 500ps cpu-sdram <500ps cpu(early)-pci: 1-4ns, center 2-6ns cpu-agp 500ps frequency generator & integrated buffers for pentium/pro tm ! 1 1 1 100 33.33 66.67 14.318 1 1 0 95.25 31.75 63.50 14.318 1 0 1 83.3 33.30 66.60 14.318 1 0 0 75 30.00 60.00 14.318 0 1 1 91.5 30.50 61.00 14.318 0 1 0 96.22 32.07 64.15 14.318 0 0 1 66.8 33.40 66.80 14.318 0 0 0 60 30.00 60.00 14.318 pci (mhz) ref, ioapic (mhz) fs2 fs1 fs0 cpu, sdram (mhz) agp (mhz) ics reserves the right to make changes in the device data identified in this publication without further notice. ics advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate. ics9148-111 third party brands and names are the property of their respective owners. pin configuration ! " # $ "% % & '' ()' # r e b m u n n i pe m a n n i pe p y tn o i t p i r c s e d 11 d d vr w pv 3 . 3 l a n i m o n , y l p p u s r e w o p l a t x , ) 2 : 0 ( f e r 2 0 f e rt u o. k c o l c e c n e r e f e r z h m 8 1 3 . 4 1 5 . 2 _ # 3 . 3 u p c 2 , 1 n i v 3 . 3 = w o l , u p c v 5 . 2 = h g i h . v 5 . 2 r o v 3 . 3 s i 2 l d d v r e h t e h w s e t a c i d n i u p c 1 t u p n i d e h c t a l . 2 , 7 2 , 2 2 , 6 1 , 9 , 3 5 4 , 9 3 , 3 3 d n gr w pd n u o r g 41 xn i k c a b d e e f d n a ) f p 3 3 ( p a c d a o l l a n r e t n i s a h , t u p n i l a t s y r c 2 x m o r f r o t s i s e r 52 xt u o d a o l l a n r e t n i s a h . z h m 8 1 3 . 4 1 y l l a n i m o n , t u p t u o l a t s y r c ) f p 3 3 ( p a c 62 d d vr w pv 3 . 3 l a n i m o n , ) 5 : 0 ( k l c i c p d n a f _ k l c i c p r o f y l p p u s 7 f _ k l c i c pt u o w e k s s n 4 - 1 h t i w s k l c u p c h t i w s u o n o r h c n y s . t u p t u o k c o l c i c p g n i n n u r e e r f # p o t s _ i c p y b d e t c e f f a t o n s i s i h t ) y l r a e u p c ( 1 s f 2 , 1 n i e h t s n i m r e t e d s n i p s f r e h t o h t i w g n o l a . t u p n i d e h c t a l . n i p t c e l e s y c n e u q e r f . s e i c n e u w e r f p g a & i c p , m a r d s , u p c 8 0 k l c i c pt u o ) y l r a e u p c ( w e k s s n 4 - 1 h t i w s k l c u p c s u o n u o r h c n y s . s t u p t u o k c o l c i c p 2 s f 2 , 1 n it u p n i d e h c t a l . n i p t c e l e s y c n e u q e r f 3 1 , 2 1 , 1 1 , 0 1) 4 : 1 ( k l c i c pt u o ) y l r a e u p c ( w e k s s n 4 - 1 h t i w s k l c u p c s u o n u o r h c n y s . s t u p t u o k c o l c i c p 4 15 d d vr w p0 p g a , z h m 8 4 , l l p d e x i f r o f y l p p u s 5 1n i r e f f u bn i. s r e f f u b m a r d s r o f n i p t u p n i 7 1 # p o t s _ u p c 1 n i e l i b o m n i ( w o l t u p n i n e h w , l e v e l 0 c i g o l t a s k c o l c ) 3 : 0 ( k l c u p c s t l a h ) 0 = e d o m , e d o m 1 1 m a r d st u ot u p t u o k c o l c m a r d s 8 1 # p o t s _ i c p 1 n i , e d o m e l i b o m n i ( w o l t u p n i n e h w , l e v e l 0 c i g o l t a s k c o l c ) 5 : 0 ( k l c i c p s t l a h ) 0 = e d o m 0 1 m a r d st u ot u p t u o k c o l c m a r d s , 4 3 , 2 3 , 1 3 , 9 2 , 8 2 8 3 , 7 3 , 5 3 ) 9 : 0 ( m a r d st u o. s t u p t u o k c o l c m a r d s 0 2 # p o t s _ p g an i t u p n i n e h w l e v e l " 0 " c i g o l t a s k c o l c ) 2 : 1 ( p g a s t l a h t u p n i s u o n o r h c n y s a s i h t 0 p g a t c e f f a t o n s e o d ) 0 = e d o m , e d o m e l i b o m n i ( w o l 9 m a r d st u ot u p t u o k c o l c m a r d s 1 2 # d pn i l a n r e t n i & l a t s y r c , o c v e h t s p o t s t u p n i n w o d r e w o p s u o n o r e h c n y s a s i h t ) 0 = e d o m , e d o m e l i b o m n i ( . w o l , e v i t c a n e h w s k c o l c 8 m a r d st u ot u p t u o k c o l c m a r d s 6 3 , 0 3 , 9 13 d d vr w p , s k c o l c z h m 8 4 , e r o c u p c , ) 1 1 : 0 ( m a r d s r o f y l p p u s . v 3 . 3 l a n i m o n 3 2a t a d sn ii r o f t u p n i a t a d 2 . t u p n i l a i r e s c 4 2k l c sn ii f o t u p n i k c o l c 2 t u p n i c 5 2 0 p g at u o y b d e t c e f f a t o n . 4 d d v y b d e r e w o p , t u p t u o t r o p c i h p a r g d e c n a v d a # p o t s _ p g a e d o m 2 , 1 n i . e d o m e l i b o m = 0 , e d o m p o t k s e d = 1 , n i p t c e l e s n o i t c n u f 1 2 & 0 2 , 8 1 , 7 1 n i p . t u p n i d e h c t a l 6 2 z h m 8 4t u o. g n i m i t b s u r o f k c o l c t u p t u o z h m 8 4 0 s f 2 , 1 n i e h t s n i m r e t e d s n i p s f r e h t o h t i w g n o l a . t u p n i d e h c t a l . n i p t c e l e s y c n e u q e r f . s e i c n e u w e r f p g a & i c p , m a r d s , u p c 4 4 , 3 4 , 1 4) 3 : 0 ( k l c u p ct u ow o l = # p o t s _ u p c f i w o l . 2 l d d v y b d e r e w o p , s t u p t u o k c o l c u p c 0 42 1 m a r d st u o. t u p t u o k c o l c m a r d s k c a b d e e f 2 4l d d vr w pl a n i m o n v 3 . 3 r o v 5 . 2 r e h t i e , ) 3 : 0 ( u p c r o f y l p p u s 7 4 , 6 4) 2 : 1 ( p g at u o. 4 d d v y b d e r e w o p , s t u p t u o t r o p c i h p a r g d e c n a v d a 8 44 d d vr w p) 2 : 0 ( p g a r o f y l p p u s ics9148-111 third party brands and names are the property of their respective owners. general description power groups ""#$%& '# ()#() "" $** +&(** ', "" $-". '# (/! "" $0#' "",$& 1( 2.34(0 ""$*5* ' 5 . 2 _ # 3 . 3 u p c l e v e l t u p n i ) a t a d d e h c t a l ( r o f d e t c e l e s r e f f u b : t a n o i t a r e p o 1d d v v 5 . 2 0d d v v 3 . 3 cpu 3.3#_2.5v buffer selector for cpuclk drivers. power management functionality mode pin - power management input control 5 2 n i p , e d o m ) t u p n i d e h c t a l ( 7 1 n i p8 1 n i p0 2 n i p1 2 n i p 0 # p o t s _ u p c ) t u p n i ( # p o t s _ i c p ) t u p n i ( # p o t s _ p g a ) t u p n i ( # d p ) t u p n i ( 1 1 1 m a r d s ) t u p t u o ( 0 1 m a r d s ) t u p t u o ( 9 m a r d s ) t u p t u o ( 8 m a r d s ) t u p t u o ( # p o t s _ p g a# p o t s _ u p c# p o t s _ i c p , p g a k l c u p c s t u p t u o k l c i c p ) 5 : 0 ( , f _ k l c i c p z h m 8 4 , f e r m a r d s d n a l a t s y r c c s o o c v) 2 : 1 ( p g a 10 1 w o l d e p p o t sg n i n n u rg n i n n u rg n i n n u rg n i n n u rg n i n n u r 111 g n i n n u rg n i n n u rg n i n n u rg n i n n u rg n i n n u rg n i n n u r 110 g n i n n u rw o l d e p p o t sg n i n n u rg n i n n u rg n i n n u rg n i n n u r 011 g n i n n u rg n i n n u rg n i n n u rg n i n n u rg n i n n u rw o l d e p p o t s 67 8!7 !!9 "9: ;9 8 8 7 / !7 < !/ !!9 8 !7 / - ! / 787 * 8 8 - ! / !/ ! / %. / 2= # =67 %.> ! ? 7 8 8 !/ 7 8 67 / / ! 8 ( ?7 !7 87/ ! 7 ! 8 8 < ! < - 8 8 * ! ? !7 8 8 ! ( !!9 8 8 > !/ ! ics9148-111 third party brands and names are the property of their respective owners. # 67 *- !!9 8 <:! <( * ! ! !9 7 7 !7 < ! 67 / 7 !!9 8 # :! 67 8 8 !< 67/ 2 / , 6 / 7 !!9 8 * !( 7 ! / @ @ 7 ! 67 / !! > ? 7 87 / ? 7 7 / / ! / 7 67* ! =/! 7? < (7 8 7 ? / 67 - > ! a ? ( 8 ! ( 7? general i 2 c serial interface information 67 7 ! /? 7 *8 8 & (! !*- *8 8 ! how to write: ! " how to read: # " controller (host) ics (slave/receiver) start bit address d3 (h) ac k byte count ack byte 0 ack byte 1 ack byte 2 ack byte 3 ack byte 4 ack byte 5 ack stop bit how to read: controller (host) ics (slave/receiver) start bit address d2 (h) ac k dummy command code ac k dummy byte count ac k byte 0 ac k byte 1 ack byte 2 ac k byte 3 ac k byte 4 ac k byte 5 ac k stop bit how to write: ics9148-111 third party brands and names are the property of their respective owners. bit pwd bit6 bit5 bit4 cpu clock pci agp 111 100 33.33 66.67 110 95.25 31.75 63.50 101 83.3 33.30 66.60 100 75 30.00 60.00 011 91.5 30.50 61.00 010 96.22 32.07 64.15 001 66.8 33.40 66.80 000 60 30.00 60.00 description must be 0 for normal operation 0 -- +/- 0.25% spread spectrum modulation 1 -- +/- 0.6% spread spectrum modulation bit 7 bit 3 bit 2 0 note 1 bit 6:4 0 - running 0 - frequency is selected by hardware select, latched inputs 1 - frequency is selected by bit 6:4 (above) must be 0 for normal operation 0 - spread spectrum center spread type. bit 1 bit 0 1 - tristate all out p uts 0 0 0 0 1 - spread spectrum down spread type. 0 - normal 1 - spread spectrum enabled !" " # $ % & ' ( serial configuration command bitmap ' # # * " + , - . * # . " " " * + , % # , ) ! b"$?5" !*+,- . - $ %' / + ' / ( ) ! # ! < 7 cb ? !7 8 ) ! # ! < 7 cb ? !7 8 t i b# n i pd w pn o i t p i r c s e d 7 t i b-1 ) d e v r e s e r ( 6 t i b-1 ) d e v r e s e r ( 5 t i b-1 ) d e v r e s e r ( 4 t i b0 41 ) t c a n i / t c a ( 2 1 m a r d s 3 t i b-1 ) d e v r e s e r ( 2 t i b1 41 ) t c a n i / t c a ( 2 k l c u p c 1 t i b3 41 ) t c a n i / t c a ( 1 k l c u p c 0 t i b4 41 ) t c a n i / t c a ( 0 k l c u p c t i b# n i pd w pn o i t p i r c s e d 7 t i b-1 ) d e v r e s e r ( 6 t i b71 ) t c a n i / t c a ( f _ k l c i c p 5 t i b-1 ) d e v r e s e r ( 4 t i b3 11 ) t c a n i / t c a ( 4 k l c i c p 3 t i b2 11 ) t c a n i / t c a ( 3 k l c i c p 2 t i b1 11 ) t c a n i / t c a ( 2 k l c i c p 1 t i b0 11 ) t c a n i / t c a ( 1 k l c i c p 0 t i b81 ) t c a n i / t c a ( 0 k l c i c p 0!,- . - $ %' / + ' / ( ics9148-111 third party brands and names are the property of their respective owners. 1! 2 ,3,- . - $ %' / + ' / ( ) ! # ! < 7 cb ? !7 8 t i b# n i pd w pn o i t p i r c s e d 7 t i b8 21 ) t c a n i / t c a ( 7 m a r d s 6 t i b9 21 ) t c a n i / t c a ( 6 m a r d s 5 t i b1 31 ) t c a n i / t c a ( 5 m a r d s 4 t i b2 31 ) t c a n i / t c a ( 4 m a r d s 3 t i b4 31 ) t c a n i / t c a ( 3 m a r d s 2 t i b5 31 ) t c a n i / t c a ( 2 m a r d s 1 t i b7 31 ) t c a n i / t c a ( 1 m a r d s 0 t i b8 31 ) t c a n i / t c a ( 0 m a r d s !2 ,3,- . - $ %' / + ' / ( 4! 5 ,- . - $ %' / + ' / ( ) ! # ! < 7cb ? !7 8 ) ! # ! < 7 cb ? !7 8 t i b# n i pd w pn o i t p i r c s e d 7 t i b5 21 ) e v i t c a n i / e v i t c a ( 0 p g a 6 t i b-1 ) d e v r e s e r ( 5 t i b-1 ) d e v r e s e r ( 4 t i b-1 ) d e v r e s e r ( 3 t i b7 11 ) t c a n i / t c a ( 1 1 m a r d s ) y l n o e d o m p o t k s e d ( 2 t i b8 11 ) t c a n i / t c a ( 0 1 m a r d s ) y l n o e d o m p o t k s e d ( 1 t i b0 21 ) t c a n i / t c a ( 9 m a r d s 0 t i b1 21 ) t c a n i / t c a ( 8 m a r d s t i b# n i pd w pn o i t p i r c s e d 7 t i b-1 ) d e v r e s e r ( 6 t i b-1 ) d e v r e s e r ( 5 t i b-1 ) d e v r e s e r ( 4 t i b7 41 ) t c a n i / t c a ( 1 p g a 3 t i b-1 ) d e v r e s e r ( 2 t i b-1 ) d e v r e s e r ( 1 t i b6 41 ) t c a n i / t c a ( 2 p g a 0 t i b21 ) t c a n i / t c a ( 0 f e r 6!7 $ &/ " # 8 ) ! # =/ a < / 8 * ! -/ ! t i b# n i pd w pn o i t p i r c s e d 7 t i b-1 ) d e v r e s e r ( 6 t i b-1 ) d e v r e s e r ( 5 t i b-1 ) d e v r e s e r ( 4 t i b-1 ) d e v r e s e r ( 3 t i b-1 ) d e v r e s e r ( 2 t i b-1 ) d e v r e s e r ( 1 t i b-1 ) d e v r e s e r ( 0 t i b-1 ) d e v r e s e r ( ics9148-111 third party brands and names are the property of their respective owners. (d(2( ,e a 7 < 8 ! 7 < ! " 8 ?( 7/ ! 67 8 ! < <8 7 7 7 !7 7 ?c ( * !7! ! 8< (7< !!7 87 7 ! 7 7 ! 7 ! !!9 1 68 7 ! 8 8 7 ( ! ! 7 7 "" 8 ! # ? / 7 0;" 8 ! <8 # 7 # < 77 *.c- 8 8 <8 8 7 ? 8 8 < 8 ! 7 !!9 8 7 > 8 & 8# 7?7! 8 7 ! & 8 # 7 7 7 ! < 8 ! 8 7 < !f 8 !& 8 < 8 8 ?7 7 7/ ! g 7 / shared pin operation - input/output pins fig. 1 67 8 7 *= 7/ ! / 67 ! 8 !7 8 7 ! < 7 7/ ! 7 ? ! !!9 8 67 / 7< 4 < ! 7 !!9 8 ( 787 7 8 8 ics9148-111 third party brands and names are the property of their respective owners. fig. 2a fig. 2b ics9148-111 third party brands and names are the property of their respective owners. agp_stop# timing diagram / % " 0 $01 /( 2345 6 , " %* %, 7 4" , "8 " 0 $01 " / " 9 * '6 02345 6 "# " " : ; ,c / .c"% !7 ? 0+-6ch /!7 7 !!9 / 7 4 70 !!9 ? ? 0+-6ch / !7 4 / 7 670* ? ?/ ? !7 78 77 87? 7 0* !/ 7 0* 0* !/ 7 0* 67 ! < /? 7.c"% !7? ics9148-111 third party brands and names are the property of their respective owners. cpu_stop# timing diagram *5+-6ch /!7 7 !!9 / 7 4 7 *5 !!9 ? ? *5+-6ch / !7 4/7 67 77*5!!9 *5+-6ch7 87 # *5!!97!!9? ! ?7 7*5!!9 67*5!!9? ?/ ? !7 78 77 87? 7 *5!!9 !/ 7 *5!!9 *5!!9 !/ 7 *5!!9 / % " 0 $ 9 0 $2345 6 , " %* %, 7 4" , "8 " 0 $ 9 " 03<= / " 9 * : 3'/> ; ics9148-111 third party brands and names are the property of their respective owners. pci_stop# timing diagram *+-6ch / !7 7 7 ** ', !!9 ? ? *+-6ch / !7 4/7 /67 77** ', !!9 *+-6ch7 87 # ** ', !!9** ', !!9 ? ? 7 7 87? 78 ** ', !!9 !/!/! / 8** !!9 !/ ** !!9 / % " 0 $01 : " 03<= ! ; 02345 6 , " %* %, 7 4" + * , "8 " 03<= / " 9 * 0 $2345 6 "# " " : ; ics9148-111 third party brands and names are the property of their respective owners. pd# timing diagram 67?? ! 7 </??? 7 87?7"h / !7 ! <? 67 8 / !7 4 7< ! ? 8? 7!!9 / 7 4 !!9 87< ! ?? b7 "h ! <?!!9 < ?< 7 87 *c !/67? !/ 7 -67?? !/ 7 7 ! 8 7 > ! > 7? ? *+-6ch *5+-6ch! i! 87?? 67%& 2.34!!91! 7 cb " 7 7 8 !( 8 7 8 7 %& !!9 7 cb / > 7 !!9 !/! ! / % " 0 $01 : " 03<= ! ; / "# " 3 1# " 7 '6 # '6 , " %* %, 7 4" , "8 " 4" " " 05 " 0, ! 9 - ' % "# #" >&8 3% #" 0 $ >&8 ics9148-111 third party brands and names are the property of their respective owners. absolute maximum ratings -/ 8 d 8 ! 0;"j , k , c 8 6 l*kd l* -8 6 ja,l*k#, l* - < 7 / ! 8 7 < ! 67 8 ! ! / ! 7 < ! 7 / 7 ! < 7 7 ! 7 ! ! %1 1 8 ! 1 /!! / electrical characteristics - input/supply/common output parameters t a = 0 - 70 o c; supply voltage v dd =3.3 v +\- 5%, v ddl = 2.5 v +/- 5% (unless otherwise stated) parameter symbol conditions min typ max units input high voltage v ih 2 v dd +0.3 v input low voltage v il v ss -0.3 0.8 v input high current i ih v in = v dd 0.1 5 a input low current i il1 v in = 0 v; inputs with no pull-up resistors -5 2.0 a input low current i il2 v in = 0 v; inputs with pull-up resistors -200 -100 a operating i dd3.3op66 select @ 66.8mhz; cl=0; all outputs running 115 160 ma supply current i dd3.3op100 select @ 100mhz; cl=0; all outputs running 140 190 ma power down current i dd3.3pd pd# = 0; full capacitive loads 150 600 a input frequency f i v dd = 3.3 v 12 14.318 16 mhz in p ut ca p acitance 1 c in logic inputs 5 pf c inx x1 & x2 pins 27 36 45 pf transition time 1 t trans to first crossing of target freq. 0.65 2 ms settlin g time 1 t s from first crossing to 1% of target freq. 0.35 3 ms clk stabilization 1 t stab from v dd = 3.3 v to 1% target freq. <1.5 2 ms t cpu-pci v t =1.5 v; f=66/100 mhz; v dd =v ddl 22.54 ns skew 1 t cpu-pci v t =1.5 v; f=83/75 mhz; v dd =v ddl 24.255 ns t agp-pci v t = 1.5 v; agp leads 400 700 ps 1 guaranteed by design, not 100% tested in production. electrical characteristics - input/supply/common output parameters t a = 0 - 70 o c; supply voltage v dd = 3.3 v +/-5%, v ddl = 2.5 v +/-5% (unless otherwise stated) parameter symbol conditions min typ max units operating i dd2.5op66 select @ 66.8mhz; c l =0; all outputs running 15 30 ma supply current i dd2.5op100 select @ 100mhz; c l =0; all outputs running 18 35 ma 1 guaranteed by design, not 100% tested in production. ics9148-111 third party brands and names are the property of their respective owners. electrical characteristics - cpu3.3 t a = 0 - 70 o c; v dd = v ddl = 3.3 v +/-5%; c l = 20 pf (unless otherwise stated) parameter symbol conditions min typ max units output high voltage v oh2b i oh = -28 ma 2.5 2.6 v output low voltage v ol2b i ol = 24 ma 0.34 0.4 v output high current i oh2b v oh =2.0 v -29 -23 ma output low current i ol2b v ol = 0.8 v 33 52 ma rise time t r2b 1 v ol = 0.4 v, v oh = 2.4 v 1 2 ns fall time t f2b 1 v oh = 2.4 v, v ol = 0.4 v 0.9 2 ns duty cycle d t2b 1 v t = 1.5 v 45 52 55 % skew t sk2b 1 v t = 1.5 v 90 175 ps vt = 1.5 v; f=66/100 mhz 150 320 ps vt = 1.5 v; f=75/83 mhz 285 550 ps 1 guaranteed by design, not 100% tested in production. 2 edge displacement of a period relative to a 10-clock-cycle rolling average period. tj srd2b 1 jitter, single edge dis p lacement2 electrical characteristics - cpu2.5 t a = 0 - 70 o c; v dd = 3.3 v +/-5%, v ddl = 2.5 v +/-5%; c l = 20 pf (unless otherwise stated) parameter symbol conditions min typ max units output high voltage v oh2b i oh = -8.0 ma 2 2.2 v output low voltage v ol2b i ol = 12 ma 0.22 0.4 v output high current i oh2b v oh =1.7 v -20 -16 ma output low current i ol2b v ol = 0.7 v 19 39 ma rise time t r2b 1 v ol = 0.4 v, v oh = 2.0 v 1 1.6 ns fall time t f2b 1 v oh = 2.0 v, v ol = 0.4 v 0.9 1.6 ns duty cycle d t2b 1 v t = 1.25 v 45 51 55 % skew t sk2b 1 v t = 1.25 v 110 175 ps jitter, single edge tj srd2b 1 vt = 1.25 v; f=66/100 mhz 170 340 ps displacement 2 vt = 1.25 v; f=75/83 mhz 310 680 ps 1 guaranteed by design, not 100% tested in production. 2 edge displacement of a period relative to a 10-clock-cycle rolling average period. ics9148-111 third party brands and names are the property of their respective owners. electrical characteristics - pciclk t a = 0 - 70 o c; v dd = 3.3 v +/-5%, v ddl = 2.5 v +/-5%; c l = 30 pf (unless otherwise stated) parameter symbol conditions min typ max units output high voltage v oh1 i oh = -28 ma 2.4 3 v output low voltage v ol1 i ol = 23 ma 0.32 0.4 v output high current i oh1 v oh = 2.0 v -60 -40 ma output low current i ol1 v ol = 0.8 v 41 54 ma rise time 1 t r1 v ol = 0.4 v, v oh = 2.4 v 1.6 2 ns fall time 1 t f1 v oh = 2.4 v, v ol = 0.4 v 1.3 2 ns duty cycle 1 d t1 v t = 1.5 v 45 51 55 % skew 1 t sk1 v t = 1.5 v 100 250 ps jitter, single edge dis p lacement2 tj srd 1 v t = 1.5 v 220 500 ps 1 guaranteed by design, not 100% tested in production. 2 edge displacement of a period relative to a 10-clock-cycle rolling average period. electrical characteristics - sdram t a = 0 - 70 o c; v dd = 3.3 v +/-5%, v ddl = 2.5 v +/-5%; c l = 30 pf (unless otherwise stated) parameter symbol conditions min typ max units output high voltage v oh3 i oh = -24 ma 2.4 2.9 v output low voltage v ol3 i ol = 23 ma 0.35 0.4 v output high current i oh3 v oh = 2.0 v -68 -40 ma output low current i ol3 v ol = 0.8 v 41 53 ma rise time t r3 1 v ol = 0.4 v, v oh = 2.4 v 1.4 2 ns fall time t f3 1 v oh = 2.4 v, v ol = 0.4 v 1.4 2 ns duty cycle d t3 1 v t = 1.5 v 48 54 60 % v t = 1.5 v, sdram 0,8,9,12 window 140 v t = 1.5 v, sdram 2,4,5,6 window 120 250 ps v t = 1.5 v, sdram 1,3,7,10,11 window 140 propagation delay t prop v t = 1.5 v 3.5 4.5 ns 1 guarenteed by design, not 100% tested in production. skew 1 t sk1 ics9148-111 third party brands and names are the property of their respective owners. electrical characteristics - agp t a = 0 - 70 o c; v dd = 3.3 v +/-5%, v ddl = 2.5 v +/-5%; c l = 30 pf (unless otherwise stated) parameter symbol conditions min typ max units output high voltage v oh1 i oh = -28 ma 2.4 3 v output low voltage v ol1 i ol = 23 ma 0.32 0.4 v output high current i oh1 v oh = 2.0 v -60 -40 ma output low current i ol1 v ol = 0.8 v 41 54 ma rise time 1 t r1 v ol = 0.4 v, v oh = 2.4 v 1.3 2 ns fall time 1 t f1 v oh = 2.4 v, v ol = 0.4 v 1.2 2 ns v t = 1.5 v, agp0 45 51 55 % v t = 1.5 v, agp1:2 48 53 58 % skew 1 t sk1 v t = 1.5 v 110 250 ps jitter, single edge v t = 1.5 v, agp0 660 1200 ps displacement 2 v t = 1.5 v, agp1:2 310 650 ps 1 guaranteed by design, not 100% tested in production. 2 edge displacement of a period relative to a 10-clock-cycle rolling average period. duty cycle 1 d t1 tj srd 1 electrical characteristics - ref0, 48mhz t a = 0 - 70 o c; v dd = 3.3 v +/-5%, v ddl = 2.5 v +/-5%; c l = 20 pf (unless otherwise stated) parameter symbol conditions min typ max units output high voltage v oh5 i oh = -16 ma 2.4 2.6 v output low voltage v ol5 i ol = 9 ma 0.24 0.4 v output high current i oh5 v oh = 2.0 v -32 -22 ma output low current i ol5 v ol = 0.8 v 16 28 ma rise time 1 t r5 v ol = 0.4 v, v oh = 2.4 v 1.5 4 ns fall time 1 t f5 v oh = 2.4 v, v ol = 0.4 v 2.1 4 ns duty cycle 1 d t5 v t = 1.5 v, ref0 50 55 60 % v t = 1.5 v, 48m 46 55 56 % jitter, single edge tj srd5 v t = 1.5 v, ref0 430 750 ps displacement 2 v t = 1.5 v, 48m 790 1200 ps v t = 1.5 v, ref0 -550 350 550 ps v t = 1.5 v, 48m -700 520 700 ps 1 guaranteed by design, not 100% tested in production. 2 edge displacement of a period relative to a 10-clock-cycle rolling average period. jitter, absolute 1 t jabs5 ics9148-111 third party brands and names are the property of their respective owners. = routed power = ground connection key (component side copper) = ground plane connection = power route connection = solder pads = clock load c3 1 clock load 2 c1 c1 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 ferrite bead vdd c2 22f/20v tantalum ferrite bead vdd c2 22f/20v tantalum 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 ground 2.5v power route 3.3v power route 3.3v power route 922! : ; ! # 58 7 8 /7*= / ! .9 ? ! 8 !? 7< ? ! ! ) ! # !!9 7 7< < #, !! ? 7 !!9 8 ;7? ! < / 8 c !/ !! ! 67/ 7 ! 7 / 8 9 ! *#'*/< / * ' m&: :"!:6 )6 n" a. * '#,&!! &=$& ! ,# aa #d)# 9!! #m&! ! ics9148-111 third party brands and names are the property of their respective owners. ssop package l o b m y s s n o i s n e m i d n o m m o c s n o i t a i r a v d n . n i m. m o n. x a m. n i m. m o n. x a m a5 9 0 .1 0 1 .0 1 1 .c a0 2 6 .5 2 6 .0 3 6 .8 4 1 a8 0 0 .2 1 0 .6 1 0 . 2 a8 8 0 .0 9 0 .2 9 0 . b8 0 0 .0 1 0 .5 3 1 0 . c5 0 0 .- 0 1 0 . ds n o i t a i r a v e e s e2 9 2 .6 9 2 .9 9 2 . ec s b 5 2 0 . 0 h0 0 4 .6 0 4 .0 1 4 . h0 1 0 .3 1 0 .6 1 0 . l4 2 0 .2 3 0 .0 4 0 . ns n o i t a i r a v e e s 0 5 8 x5 8 0 .3 9 0 .0 0 1 . ordering information ics9148 y f-111 !"#$% & %' () ?@335 - 2 $ ? ! ? 7 7 < *+ %() % & , 03 / @ 3 '! %1 ' ics xxxx y f - ppp ics reserves the right to make changes in the device data identified in this publication without further notice. ics advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate. |
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